1. Field of the Invention
The present invention relates to a method of forming a pattern of a multilayer type semiconductor device, and more particularly, it is concerned with a method of forming a pattern of a multilayer type semiconductor device, which allows improvement of accuracy in overlaying respective layers.
2. Description of the Background Art
Since the minimum processing size of a semiconductor device has been reduced from 1.0 .mu.m to 0.8 .mu.m and further down to 0.5 .mu.m, an accuracy in overlaying respective layers of a semiconductor device formed by stacking multiple layers has become more important. At present, an overlaying accuracy of 1/3-1/4 of the minimum processing size is required.
In the meantime, as to reduction projection aligners, 1:5 reduction projection aligners have come to be used instead of 1:1 projection aligners.
In a method of exposure utilizing reduction projection aligners, first an exposure light emitted from a light source transmits through a photomask in which a predetermined pattern is formed on a transparent substrate, and then is reduced by a reduction lens having a high resolution (mainly a reduction ratio of 1:5) for projecting the pattern image onto regions arranged in a matrix, so-called chip regions 310, of a semiconductor wafer 400 (see FIG. 20). Then, by moving the wafer repeatedly in X and Y directions, i.e., a step and repeat operation, the pattern is exposed on chip regions on the entire surface of the wafer.
Since exposure of the pattern is carried out for every chip forming region on the semiconductor wafer in this exposure method, the number of the semiconductor wafers capable of being processed in a unit time is reduced. However, there are advantages in this exposure method as follows:
i) a resolution of the pattern is superior, PA1 ii) positioning can be carried out with a high accuracy because of a laser gauge interferometer used for controlling a position of the semiconductor wafer, PA1 iii)position control can be carried out every time the pattern image is exposed on the chip region; the focussing position of the pattern image can be adjusted every time exposure is carried out on the chip region, and PA1 iv) insufficient exposure due to the photomask will not occur unless the photomask has defects.
The above mentioned exposure method utilizing reduction projection aligners is disclosed in, for example, Japanese Patent Laying-Open No. 1-283927. The exposure method utilizing the reduction projection aligner will be described in brief below with referring to the drawings.
First referring to FIG. 21, a reduction projection aligner 500 includes a mercury lamp 550 surrounded by an oval mirror 551, a reflection mirror 552, an integrator 553, a reflection mirror 554, a condenser lens 555, a photomask 556, a reduction lens 557, a semiconductor wafer 558, and an X-Y stage 559.
An exposure light 550a emitted from mercury lamp 550 is collected by oval mirror 551 and directed to reflection mirror 552. Exposure light 550a is reflected from reflection mirror 552 to enter on integrator 553. Integrator 553 includes a plurality of fly eye lenses (not shown) for uniforming the light intensity of exposure light 550a.
Exposure light 550a transmitted through integrator 553 is reflected from reflection mirror 554 to be incident on condenser lens 555. Exposure light 550a is then directed to photomask 556 in which a predetermined pattern is formed. Exposure light 550a transmitted through integrator 553 is uniformly directed to the entire surface of photomask 556 by condenser lens 555.
Exposure light 550a transmitted through photomask 556 is reduced at a predetermined reduction ratio (1:m) by reduction lens 557 and the image is projected onto the surface of semiconductor wafer 558 so that a resist film on semiconductor wafer 558 is exposed.
Next referring to FIG. 22, X-Y stage 559 moves and stops repeatedly by a prescribed distance in X direction or Y direction, and when the X-Y stage stops, a predetermined pattern image is exposed on the predetermined chip region 310 with exposure light 550a exposing a resist film on the surface of semiconductor wafer 400. A plurality of chip regions 310 arranged in a matrix are thus formed on semiconductor wafer 400.
Next, description will be made on a method of exposing a semiconductor device formed by stacking a first layer having a first pattern and a second layer having a second pattern, utilizing the above-described reduction projection aligner 500.
Referring to FIG. 23, a first photomask 70 having a first pattern and a second photomask 71 having a second pattern, both used in the exposure method, are described. Alignment mark patterns 70a, 70b, 70c, and 70d (71a, 71b, 71c, and 71d) are formed at predetermined positions in regions except for pattern forming regions on first photomask 70 and second photomask 71, respectively.
In the meantime, a first layer and a first resist film covering the first layer are formed on the semiconductor wafer. With a first exposure apparatus provided with first photomask 70, the first pattern image is exposed on the surface of the first resist film. Then, the first resist film is developed, and the first layer is patterned using the first resist film as a mask.
Semiconductor wafer 400 is taken from the first exposure apparatus and a second layer and a second resist film are formed on the semiconductor wafer. After that, semiconductor wafer 300 is placed on a second exposure apparatus.
After that, positions of alignment marks 70A-70D formed on the first layer are detected. Detection of those alignment marks 70A-70D is carried out by optical measurement such as detection using a laser beam in the dark field, a multicolor light in the light field, or a heterodyne interference light.
Referring to FIG. 24, a brief description will be given for an alignment mark detector 600 using the laser beam in the dark field for detection. First semiconductor wafer 400 is placed at a predetermined position on an X-Y stage 610. X-Y stage 610 moves in X and Y directions with recognizing coordinates accurately with the laser interferometer. A laser beam emitted from an LSA laser 620 passes through a projection lens 630 to be condensed onto each alignment mark (70A-70D) formed on chip region 310 on the semiconductor wafer. The light reflected from those alignment marks (70A-70D) are introduced to an accurately-disposed detector so that only refraction components are detected for identifying position coordinates of alignment marks (70A-70D).
The exposure of the second pattern image is then carried out based on alignment marks 70A-70D of which positions have been detected as above, and subsequently, development of the second resist film and patterning of the second layer are carried out.
If it is desired to stack additional layers having predetermined patterns, the positions of the alignment marks formed on the layer directly under such a lower layer of which overlaying accuracy is important should be detected, and the exposure of the predetermined pattern image can be carried out based on those alignment marks.
However, there is a problem in the above-described exposure method as follows. Referring to FIG. 25, when the first pattern is exposed onto the first layer using the first exposure apparatus, an exposure error is incurred by the first exposure apparatus. A major reason for this error is called a lens distortion in which the pattern image is deformed by the lens.
Therefore, alignment marks (70A-70D) are originally designed to be formed on the positions indicated by dotted lines in the drawing. In practice, however, alignment marks (70A'-70D') are formed on the positions indicated by solid lines during exposure.
If alignment is carried out based on those alignment marks (70A'-70D') which are offset from the design positions, a pattern on a layer to be aligned will be moved in a direction alignment marks are offset. This leads to a significant alignment offset between respective layers, so that miniaturization requirement of the semiconductor device cannot be attained.
One way to solve such a problem is, for example, the exposure method disclosed in Japanese Patent Laying-Open No. 63-81818. This exposure method is aimed to measure in advance the lens distortion involved in the exposure apparatus. This exposure method will be described below referring to FIGS. 26-29 showing manufacturing steps.
Referring to FIG. 26, a first pattern and first alignment mark patterns 600a-600e are included in predetermined positions of a photomask 600. A first layer is formed on a semiconductor wafer 400 provided for measurement of the lens distortion, and then a first resist film is formed on the first layer.
Using the photomask 600, images of the first alignment mark patterns 600A-600E are exposed on the resist film as shown in FIG. 27.
Referring to FIG. 28, photomask 600 is covered by a blind 700 for exposing only alignment mark pattern 600e. Using the photomask 600, pattern images of alignment marks 700A-700E for measuring errors are exposed onto the design positions of alignment marks 600A-600E, by the position control of the stage having semiconductor wafer 400 placed thereon.
Referring to FIG. 29, after development of the resist film, the first layer is patterned using the resist film as a mask for forming first alignment marks 600A-600E and alignment marks 700A-700E provided for measuring errors. At this time, if there is no error incurred by the exposure apparatus, alignment marks 700A-700E for measuring errors are formed right on alignment marks 600A-600E.
However, errors such as lens distortion involved in the exposure apparatus are sensitive to the usage environment including temperature, humidity and the like and change with the environment. Therefore, it has been very difficult to control those errors involved in the exposure apparatus.
Accordingly, in the semiconductor device in which layers are stacked, it has been difficult to overlay respective layers with high accuracy.